View HM66AEB18202_259896.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HM66AEB36102/HM66AEB18202 HM66AEB9402
36-Mbit DDR II SRAM 2-word Burst
REJ03C0046-0001Z (Previous ADE-203-1365 (Z) Rev. 0.0) Preliminary Rev.0.01 Apr.28.2004
Description
The HM66AEB36102 is a 1,048,576-word by 36-bit, the HM66AEB18202 is a 2,097,152-word by 18-bit, and the HM66AEB9402 is a 4,194,304-word by 9-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K) and are latched on the positive edge of K and K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Renesas Technology's Sales Dept. regarding specifications.
Rev.0.01, Apr.28.2004, page 1 of 28
HM66AEB36102/18202/9402
Features
* 1.8 V 0.1 V power supply for core (VDD) * 1.4 V to VDD power supply for I/O (VDDQ) * DLL circuitry for wide output data valid window and future frequency scaling * Pipelined double data rate operation * Common data input/output bus * Two-tick burst for low DDR transaction size * Two input clocks (K and K) for precise DDR timing at clock rising edges only * Two output clocks (C and C) for precise flight time and clock skew matching-clock and data delivered together to receiving device * Internally self-timed write control * Clock-stop capability with s restart * User programmable impedance output * Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/ 5.0 ns (200 MHz)/6.0 ns (167 MHz) * Simple control logic for easy depth expansion * JTAG boundary scan
Ordering Information
Type No. HM66AEB36102BP-30 HM66AEB36102BP-33 HM66AEB36102BP-40 HM66AEB36102BP-50 HM66AEB36102BP-60 HM66AEB18202BP-30 HM66AEB18202BP-33 HM66AEB18202BP-40 HM66AEB18202BP-50 HM66AEB18202BP-60 HM66AEB9402BP-30 HM66AEB9402BP-33 HM66AEB9402BP-40 HM66AEB9402BP-50 HM66AEB9402BP-60 Organization 1-M word x 36-bit Cycle time 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns Clock frequency 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Package Plastic FBGA 165-pin (BP-165A)
2-M word x 18-bit
4-M word x 9-bit
Rev.0.01, Apr.28.2004, page 2 of 28
HM66AEB36102/18202/9402
Pin Arrangement (HM66AEB36102) 165PIN-BGA
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 SA DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW1 BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 NC NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI
(Top view)
Pin Arrangement (HM66AEB18202) 165PIN-BGA
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 SA NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI
(Top view)
Rev.0.01, Apr.28.2004, page 3 of 28
HM66AEB36102/18202/9402
Pin Arrangement (HM66AEB9402) 165PIN-BGA
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS NC NC NC NC NC NC VREF NC NC DQ7 NC NC NC TCK 3 SA NC NC NC DQ5 NC DQ6 VDDQ NC NC NC NC NC DQ8 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NC NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC NC NC NC VREF DQ2 NC NC NC NC NC TMS 11 CQ DQ4 NC NC DQ3 NC NC ZQ NC NC DQ1 NC NC DQ0 TDI
(Top view) Note: Note that 6C is not SA0. The x9 product does not permit random start address on the least significant address bit. SA0 = 0 at the start of each address.
Notes on Usage
* Power-on initialization cycles are required for all operations, including JTAG functions, to become normal. * Clock recovery initialization cycles are required for read/write operations to become normal. * Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 10% is 250 typical. The total external capacitance of ZQ ball must be less than 7.5 pF.
Rev.0.01, Apr.28.2004, page 4 of 28
HM66AEB36102/18202/9402
Pin Descriptions
Name SA0 SA I/O type Descriptions Input Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. All transactions operate on a burst-of-two words (one clock period of bus activity). SA0 is used as the lowest address bit for burst READ and burst WRITE operations permitting a random burst start address on x18 and x36 devices. These inputs are ignored when device is deselected. Synchronous load: This input is brought low when a bus cycle sequence is to be defined. This definition includes address and READ / WRITE direction. All transactions operate on a burst-of-two data (one clock period of bus activity). Synchronous read / write input: When LD is low, this input designates the access type (READ when R/W is high, WRITE when R/W is low) for the loaded address. R/W must meet the setup and hold times around the rising edge of K. Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and K for each of the two rising edges comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of K. K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. These balls cannot remain VREF level. Output clock: This clock pair provides a user-controlled means of tuning device output data. The rising edge of C is used as the output timing reference for first output data. The rising edge of C is used as the output timing reference for second output data. Ideally, C is 180 degrees out of phase with C. C and C may be tied high to force the use of K and K as the output reference clocks instead of having to provide C and C clocks. If tied high, C and C must remain high and not to be toggled during device operation. These balls cannot remain VREF level. DLL disable: When low, this input causes the DLL to be bypassed for stable, low frequency operation. Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG function is not used in the circuit. IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not used in the circuit.
LD
Input
R/W
Input
BW BWn
Input
K, K
Input
C, C
Input
DOFF ZQ
Input Input
TMS TDI TCK
Input Input
Rev.0.01, Apr.28.2004, page 5 of 28
HM66AEB36102/18202/9402
Name DQ0 to DQn I/O type Descriptions Input/ output Synchronous data I/Os: Input data must meet setup and hold times around the rising edges of K and K. Output data is synchronized to the respective C and C, or to the respective K and K if C and C are tied high. The x9 device uses DQ0 to DQ8. Remaining signals are NC. The x18 device uses DQ0 to DQ17. Remaining signals are NC. The x36 device uses DQ0 to DQ35.
CQ, CQ
Output Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when DQ tri-states. Output IEEE 1149.1 test output: 1.8 V I/O level. Supply Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. Supply Power supply: Isolated output buffer supply. Nominally 1.5 V. 1.8 V is also permissible. See DC Characteristics and Operating Conditions for range. Supply Power supply: Ground HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise margin. Provides a reference voltage for the HSTL input buffers. No connect: These signals are internally connected. These signals may be connected to ground to improve package heat dissipation.
TDO VDD VDDQ VSS VREF NC Note:
1. All power supply and ground balls must be connected for proper operation of the device.
Rev.0.01, Apr.28.2004, page 6 of 28
HM66AEB36102/18202/9402
Block Diagram (HM66AEB36102)
SA0 20 Address Registry & Logic Burst Logic SA0' SA0'' Output SA0''' Control Logic ZQ
SA
20
LD
R/W K
LD BW0 BW1 BW2 BW3
K
R/W
WRITE Register
Output Register
2 36
WRITE Driver
Output Buffer Output Select
Sense Amps
Data Registry & Logic 36
CQ, CQ DQ0-35
72 K
Memory Array
MUX
72 C
72
K
C, C or K, K
Block Diagram (HM66AEB18202)
SA0 21 Address Registry & Logic Burst Logic SA0' SA0'' Output SA0''' Control Logic ZQ
SA
21
LD
R/W K R/W
WRITE Register
Output Register
LD BW0 BW1
K
2 18
WRITE Driver
Output Buffer Output Select
Sense Amps
Data Registry & Logic 18
CQ, CQ DQ0-17
36 K
Memory Array
MUX
36 C
36
K
C, C or K, K
Rev.0.01, Apr.28.2004, page 7 of 28
HM66AEB36102/18202/9402
Block Diagram (HM66AEB9402)
SA 21 Address Registry 21 & Logic ZQ R/W
LD
R/W K
LD BW
K
WRITE Register
Output Register
2 9
WRITE Driver
Output Buffer Output Select
Data Registry & Logic 9
CQ, CQ DQ0-8
Sense Amps
18 K
Memory Array
MUX
18 C
18
K
C, C or K, K
Rev.0.01, Apr.28.2004, page 8 of 28
HM66AEB36102/18202/9402
Burst Sequence
Linear Burst Sequence Table (HM66AEB36102/18202)
SA0 External address 1st internal burst address 0 1 SA0 1 0
Truth Table
Operation WRITE cycle Load address, input write data on consecutive K and K rising edges K LH LD L R/W W L DQ Data in Input data Input clock READ cycle Load address, read data on consecutive C and C rising edges LH L H Data out Output data Output clock NOP (No operation) STANDBY (Clock stopped) LH Stopped H x x x High-Z Previous state Q(A1) C(t+1) Q(A2) C(t+2) D(A1) K(t+1) D(A2) K(t+1)
Notes: 1. H: high level, L: low level, x: don't care, : rising edge. 2. Data inputs are registered at K and K rising edges. Data outputs are delivered at C and C rising edges, except if C and C are high, then data outputs are delivered at K and K rising edges. 3. LD and R/W must meet setup/hold times around the rising edges (low to high) of K and are registered at the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. When clocks are stopped, the following cases are recommended; the case of K = low, K = high, C = low and C = high, or the case of K = high, K = low, C = high and C = low. This condition is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst address in accordance with the linear burst sequence.
Rev.0.01, Apr.28.2004, page 9 of 28
HM66AEB36102/18202/9402
Byte Write Truth Table
(HM66AEB36102)
Operation Write D0 to D35 K LH Write D0 to D8 LH Write D9 to D17 LH Write D18 to D26 LH Write D27 to D35 LH Write nothing LH K LH LH LH LH LH LH BW0 L L L L H H H H H H H H BW1 L L H H L L H H H H H H BW2 L L H H H H L L H H H H BW3 L L H H H H H H L L H H
Notes: 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. BW0 to BW3 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.
(HM66AEB18202)
Operation Write D0 to D17 K LH Write D0 to D8 LH Write D9 to D17 LH Write nothing LH K LH LH LH LH BW0 L L L L H H H H BW1 L L H H L L H H
Notes: 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. BW0 and BW1 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.
Rev.0.01, Apr.28.2004, page 10 of 28
HM66AEB36102/18202/9402 (HM66AEB9402)
Operation Write D0 to D8 K LH Write nothing LH K LH LH BW L L H H
Notes: 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. BW can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.
Bus Cycle State Diagram
LD = L LD = H, Count = 2
LD = L, Count = 2
WRITE DOUBLE Count = Count + 2
R/W = L LOAD NEW ADDRESS Count = 0 R/W = H
LD = H
NOP
LD = L, Count = 2
READ DOUBLE Count = Count + 2 Supply voltage provided
LD = H, Count = 2
POWER UP
Notes: 1. SA0 is internally advanced in accordance with the burst order table. Bus cycle is terminated at the end of this sequence (burst count = 2). 2. State machine control timing sequence is controlled by K.
Rev.0.01, Apr.28.2004, page 11 of 28
HM66AEB36102/18202/9402
Absolute Maximum Ratings
Parameter Input voltage on any ball Input/output voltage Core supply voltage Output supply voltage Junction temperature Storage temperature Symbol VIN VI/O VDD VDDQ Tj TSTG Rating -0.5 to VDD + 0.5 (2.5 V max.) -0.5 to VDDQ + 0.5 (2.5 V max.) -0.5 to 2.5 -0.5 to VDD +125 (max) -55 to +125 Unit V V V V C C Notes 1, 4 1, 4 1, 4 1, 4
Notes: 1. All voltage is referenced to VSS. 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the instantaneous value of VDDQ.
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Power supply voltage -- core Power supply voltage -- I/O Input reference voltage -- I/O Input high voltage Input low voltage Symbol VDD VDDQ VREF VIH (DC) VIL (DC) Min 1.7 1.4 0.68 VREF + 0.1 -0.3 Typ 1.8 1.5 0.75 Max 1.9 VDD 0.95 VDDQ + 0.3 VREF - 0.1 Unit V V V V V 1 2, 3 2, 3 Notes
Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF. 2. Overshoot: VIH (AC) VDDQ + 0.5 V for t tKHKH/2 Undershoot: VIL (AC) -0.5 V for t tKHKH/2 Power-up: VIH VDDQ + 0.3 V and VDD 1.7 V and VDDQ 1.4 V for t 200 ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). 3. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing parameters.
Rev.0.01, Apr.28.2004, page 12 of 28
HM66AEB36102/18202/9402
DC Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V)
HM66AEB36102/HM66AEB18202 HM66AEB9402 -30 Parameter Operating supply current (READ / WRITE) Symbol Max -33 -40 -50 -60 Unit Notes
(x9 / x18) (x36)
IDD IDD
770 880
720 800
630 700
540 600
480 520
mA 1, 2, 3 mA 1, 2, 3
Standby supply current (NOP)
(x9 / x18 / x36)
ISB1
350
330
300
280
260
mA 2, 4, 5
Parameter Input leakage current
Symbol Min ILI VOH (Low) VOH -2 -2 VDDQ - 0.2 VDDQ/2 - 0.08 VSS VDDQ/2 - 0.08
Max 2 2 VDDQ VDDQ/2 + 0.08 0.2 VDDQ/2 + 0.08
Unit Test conditions Notes A A V V V V |IOH| 0.1 mA Notes6 IOL 0.1 mA Notes7 10 11 8, 9 8, 9 8, 9 8, 9
Output leakage current ILO Output high voltage
Output low voltage
VOL (Low) VOL
Notes: 1. 2. 3. 4. 5.
All inputs (except ZQ, VREF) are held at either VIH or VIL. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. Operating supply currents are measured at 100% bus utilization. All address / data inputs are static at either VIN > VIH or VIN < VIL. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed. 6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 8. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 9. HSTL outputs meet JEDEC HSTL Class I and Class II standards. 10. 0 VIN VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball). 11. 0 VOUT VDDQ (except TDO ball), output disabled.
Rev.0.01, Apr.28.2004, page 13 of 28
HM66AEB36102/18202/9402
Capacitance (Ta = +25C, f = 1.0 MHz, VDD = 1.8 V, VDDQ = 1.5 V)
Parameter Input capacitance Clock input capacitance Input/output capacitance (DQ, ZQ) Symbol Min CIN CCLK CI/O Typ 4 5 6 Max 5 6 7 Unit pF pF pF Test conditions VIN = 0 V VCLK = 0 V VI/O = 0 V
Notes: 1. These parameters are sampled and not 100% tested. 2. Except JTAG (TCK, TMS, TDI, TDO) pins.
AC Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V)
Test Conditions Input waveform (Rise/fall time 0.3 ns)
1.25 V 0.75 V 0.25 V Test points 0.75 V
Output waveform
VDDQ/2
Test points
VDDQ/2
Output load condition
VDDQ/2 0.75 V VREF Zo = 50 SRAM DQ 250 ZQ 50
Rev.0.01, Apr.28.2004, page 14 of 28
HM66AEB36102/18202/9402 Operating Conditions
Parameter Input high voltage Input low voltage Notes: 1. 2. 3. Symbol VIH (AC) VIL (AC) Min VREF + 0.2 Typ Max VREF - 0.2 Unit V V Notes 1, 2, 3, 4 1, 2, 3, 4
4.
All voltages referenced to VSS (GND). These conditions are for AC functions only, not for AC parameter test. Overshoot: VIH (AC) VDDQ + 0.5 V for t tKHKH/2 Undershoot: VIL (AC) -0.5 V for t tKHKH/2 Power-up: VIH VDDQ + 0.3 V and VDD 1.7 V and VDDQ 1.4 V for t 200 ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC).
Rev.0.01, Apr.28.2004, page 15 of 28
HM66AEB36102/18202/9402
HM66AEB36102/HM66AEB18202 HM66AEB9402 -30 Parameter Symbol Min 3.00 Max 3.47 -33 Min 3.30 Max 4.20 -40 Min 4.00 Max 5.25 -50 Min 5.00 -60 Max Min 6.30 6.00 Max 7.88 Unit Notes ns
Average clock tKHKH cycle time (K, K, C, C) Clock phase jitter (K, K, C, C) tKC var
0.20
0.20
0.20
0.20
0.20
ns
3
Clock high time tKHKL (K, K, C, C) Clock low time tKLKH (K, K, C, C) Clock to clock tKH/KH (K to K, C to C) Clock to clock t/KHKH (K to K, C to C) Clock to data tKHCH clock (K to C, K to C) DLL lock time (K, C)
1.20 1.20 1.35 1.35 0
1.30
1.32 1.32 1.49 1.49 0
1.45
1.60 1.60 1.80 1.80 0
1.80
2.00 2.00 2.20 2.20 0

2.40 2.40 2.70 2.70
2.80
ns ns ns ns ns
2.30 0
tKC lock 1,024 0.45
1,024 30 0.45
1,024 30 0.45
1,024 30
1,024 30 0.50 0.50
Cycle 2 ns ns ns ns 7
K static to DLL tKC reset 30 reset C, C high to output valid C, C high to output hold C, C high to echo clock valid tCHQV tCHQX tCHCQV
0.45 -0.50
-0.45 0.45
-0.45 0.45
-0.45 0.45
-0.45
0.45
C, C high to tCHCQX echo clock hold CQ, CQ high to tCQHQV output valid CQ, CQ high to tCQHQX output hold C, C high to output high-Z C, C high to output low-Z tCHQZ tCHQX1
-0.45 0.25
-0.45 0.27
-0.45 0.30
-0.45
-0.50
0.40 0.50
ns ns ns ns ns 4, 7 4, 7 5 5
0.35 -0.40
-0.25 0.45
-0.27 0.45
-0.30 0.45
-0.35
0.45 -0.50
-0.45
-0.45
-0.45
-0.45
Rev.0.01, Apr.28.2004, page 16 of 28
HM66AEB36102/18202/9402
HM66AEB36102/HM66AEB18202 HM66AEB9402 -30 Parameter Symbol Min 0.40 0.40 Max -33 Min 0.40 0.40 Max -40 Min 0.50 0.50 Max -50 Min 0.60 0.60 Max -60 Min 0.70 0.70 Max Unit Notes ns ns 1 1
Address valid tAVKH to K rising edge Control inputs tIVKH valid to K rising edge Data-in valid to tDVKH K, K rising edge K rising edge to tKHAX address hold K rising edge to tKHIX control inputs hold tKHDX K, K rising edge to data-in hold
0.28
0.30
0.35
0.40
0.50
ns
1
0.40 0.40

0.40 0.40

0.50 0.50

0.60 0.60

0.70 0.70

ns ns
1 1
0.28
0.30
0.35
0.40
0.50
ns
1
Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept inactive during these cycles. 3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations. 5. Transitions are measured 100 mV from steady-state voltage. 6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQZ less than tCHQV. 7. These parameters are sampled. Remarks: 1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 2. Control input signals may not be operated with pulse widths less than tKHKL (min). 3. If C, C are tied high, K, K become the references for C, C timing parameters. 4. VDDQ is +1.5 V DC. 5. Control signals are LD, R/W, BW, BW0, BW1, BW2 and BW3.
Rev.0.01, Apr.28.2004, page 17 of 28
HM66AEB36102/18202/9402
Timing Waveforms
Read and Write Timing
NOP READ READ NOP (burst of 2) (burst of 2) NOP WRITE WRITE READ (burst of 2) (burst of 2) (burst of 2)
1 K
2
tKHKH
3
4
5
6
7
8
9
10
tKHKL tKLKH
tKH/KH
t/KHKH
K LD
tIVKH R/W tAVKH tKHAX Address
A0 A1 A2 A3 A4
tKHIX
tKHDX tDVKH DQ
Qx2
Q01 Q02 Q11 Q12
tKHDX tDVKH
Q41 Q42
D21 D22 D31 D32
tCHQX1 tKHCH CQ tKHCH tCHQV
tCHQX tCHQV
tCQHQX tCHQZ tCHQX tCQHQV
tCHCQX tCHCQV tCHCQX tCHCQV
CQ
C
C
tKHKL tKLKH tKHKH tKH/KH t/KHKH
Notes: 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc. 2. Outputs are disable (high-Z) one clock cycle after a NOP. 3. In this example, if address A4 = A3, then data Q41 = D31, Q42 = D32. Write data is forwarded immediately as read results. 4. To control read and write operations, BW signals must operate at the same timing as Data in. 5. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention.
Rev.0.01, Apr.28.2004, page 18 of 28
HM66AEB36102/18202/9402
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1k resistor. TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O TCK TMS TDI Pin assignments 2R 10R 11R Description Test clock input. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. Test mode select. This is the command input for the TAP controller state machine. Test data input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. Test data output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
TDO
1R
Note: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.
Rev.0.01, Apr.28.2004, page 19 of 28
HM66AEB36102/18202/9402
TAP DC Operating Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V)
Parameter Input high voltage Input low voltage Input leakage current Output leakage current Output low voltage Symbol VIH VIL ILI ILO VOL1 VOL2 Output high voltage Notes: 1. 2. 3. 4. VOH1 VOH2 Min +1.3 -0.3 -5.0 -5.0 1.6 1.4 Max VDD + 0.3 +0.5 +5.0 +5.0 0.2 0.4 Unit V V A A V V V V 0 V VIN VDD 0 V VIN VDD, output disabled IOLC = 100 A IOLT = 2 mA |IOHC| = 100 A |IOHT| = 2 mA Conditions
All voltages referenced to VSS (GND). Power-up: VIH VDDQ + 0.3 V and VDD +1.7 V and VDDQ +1.4 V for t 200 ms. In "EXTEST" mode and "SAMPLE" mode, VDDQ is nominally 1.5 V. ZQ: VIH = VDDQ.
Rev.0.01, Apr.28.2004, page 20 of 28
HM66AEB36102/18202/9402
TAP AC Test Condition
* Temperature * Input timing measurement reference levels * Input pulse levels * Input rise/fall time * Output timing measurement reference levels * Test load termination supply voltage (VTT) * Output load Input waveform
1.8 V 0.9 V 0V Test points 0.9 V
0C Ta +70C 0.9 V 0 V to 1.8 V 1.0 ns 0.9 V 0.9 V See figures
Output waveform
0.9 V
Test points
0.9 V
Output load
VTT = 0.9 V
50 Zo = 50 TDO 20 pF
External load at test
Rev.0.01, Apr.28.2004, page 21 of 28
HM66AEB36102/18202/9402
TAP AC Operating Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V)
Parameter Test clock cycle time Test clock high pulse width Test clock low pulse width Test mode select setup Test mode select hold Capture setup Capture hold TDI valid to TCK high TCK high to TDI invalid TCK low to TDO unknown TCK low to TDO valid Note: Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tCS tCH tDVTH tTHDX tTLQX tTLQV Min 100 40 40 10 10 10 10 10 10 0 Max 20 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 Note
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP Controller Timing Diagram
tTHTH TCK tMVTH TMS tTHMX TDI tTHDX TDO tCS PI (SRAM) tCH tTLQX tTLQV tDVTH tTHTL tTLTH
Test Access Port Registers
Register name Instruction register Bypass register ID register Boundary scan register Length 3 bits 1 bit 32 bits 109 bits Symbol IR [2:0] BP ID [31:0] BS [109:1]
Rev.0.01, Apr.28.2004, page 22 of 28
HM66AEB36102/18202/9402
TAP Controller Instruction Set
IR2 0 IR1 0 IR0 0 Instruction EXTEST Description The EXTEST instruction allows circuitry external to the component package to be tested. Boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the Update-IR state of EXTEST, the output driver is turned on and the PRELOAD data is driven onto the output balls. The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO balls in shiftDR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. If the SAMPLE-Z instruction is loaded in the instruction register, 3, 4 all RAM outputs are forced to an inactive drive state (high-Z), moving the TAP controller into the capture-DR state loads the data in the RAMs input into the boundary scan register, and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. The RESERVED instructions are not implemented but are reserved for future use. Do not use these instructions. When the SAMPLE instruction is loaded in the instruction 3 register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable input will not harm the device, repeatable results cannot be expected. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO balls. Notes 1, 2, 3
0
0
1
IDCODE
0
1
0
SAMPLE-Z
0 1
1 0
1 0
RESERVED SAMPLE (/PRELOAD)
1 1 1
0 1 1
1 0 1
RESERVED RESERVED BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
Rev.0.01, Apr.28.2004, page 23 of 28
HM66AEB36102/18202/9402
Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded. 2. After performing EXTEST, power-up conditions are required in order to return part to normal operation. 3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. 4. Clock recovery initialization cycles are required to return from the SAMPLE-Z instruction.
ID Register
Part
HM66AEB36102 HM66AEB18202 HM66AEB9402
Revision number (31:29)
000 000 000
Type number (28:12)
00010011010000000 00010010010000000 00010000010000000
Vendor JEDEC code (11:1)
01000100011 01000100011 01000100011
Start bit (0)
1 1 1
Rev.0.01, Apr.28.2004, page 24 of 28
HM66AEB36102/18202/9402
Boundary Scan Order
Signal names Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Ball ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E x9 C C SA SA SA SA SA SA SA DQ0 NC NC NC NC NC NC NC DQ1 NC NC NC NC NC NC NC DQ2 NC ZQ NC NC NC NC NC NC DQ3 x18 C C SA SA SA SA SA SA SA DQ0 NC NC NC DQ1 NC NC NC DQ2 NC NC NC DQ3 NC NC NC DQ4 NC ZQ NC NC DQ5 NC NC NC DQ6 x36 C C SA SA SA SA SA SA SA DQ0 DQ9 NC NC DQ11 DQ10 NC NC DQ2 DQ1 NC NC DQ3 DQ12 NC NC DQ13 DQ4 ZQ NC NC DQ5 DQ14 NC NC DQ6 Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Ball ID 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D Signal names x9 NC NC NC NC NC NC NC DQ4 NC NC NC CQ SA SA SA SA SA LD NC BW K K NC NC R/W SA SA SA VSS CQ NC NC NC NC NC x18 NC NC NC DQ7 NC NC NC DQ8 NC NC NC CQ SA SA SA SA SA0 LD NC BW0 K K NC BW1 R/W SA SA SA VSS CQ DQ9 NC NC NC DQ10 x36 DQ15 NC NC DQ17 DQ16 NC NC DQ8 DQ7 NC NC CQ NC SA SA SA SA0 LD BW1 BW0 K K BW3 BW2 R/W SA SA SA VSS CQ DQ27 DQ18 NC NC DQ19
Rev.0.01, Apr.28.2004, page 25 of 28
HM66AEB36102/18202/9402
Signal names Bit # 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Ball ID 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K x9 NC NC NC DQ5 NC NC NC NC NC NC NC DQ6 NC DOFF NC NC NC NC NC x18 NC NC NC DQ11 NC NC NC DQ12 NC NC NC DQ13 NC DOFF NC NC DQ14 NC NC x36 DQ28 NC NC DQ20 DQ29 NC NC DQ30 DQ21 NC NC DQ22 DQ31 DOFF NC NC DQ23 DQ32 NC Bit # 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Ball ID 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R
Signal names x9 DQ7 NC NC NC NC NC NC NC DQ8 NC NC NC SA SA SA SA SA SA INTERNAL x18 DQ15 NC NC NC DQ16 NC NC NC DQ17 NC NC NC SA SA SA SA SA SA INTERNAL x36 DQ33 DQ24 NC NC DQ25 DQ34 NC NC DQ26 DQ35 NC NC SA SA SA SA SA SA INTERNAL
90 1K NC NC NC Note: In boundary scan mode, 1. Clock balls (K / K, C / C) are referenced to each other and must be at opposite logic levels for reliable operation. 2. CQ and CQ data are synchronized to the respective C and C (except EXTEST, SAMPLE-Z). 3. If C and C tied high, CQ is generated with respect to K and CQ is generated with respect to K (except EXTEST, SAMPLE-Z). 4. ZQ must be driven to VDDQ supply to ensure consistent results.
Rev.0.01, Apr.28.2004, page 26 of 28
HM66AEB36102/18202/9402
TAP Controller State Diagram
1
Test-LogicReset 0
0
Run-Test/ Idle
1
SelectDR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0
1
SelectIR-Scan 0 1 Capture-IR 0 0 Shift-IR 1
1
0 1
1
Exit1-IR 0 0 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0
0
Notes: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK.
Rev.0.01, Apr.28.2004, page 27 of 28
HM66AEB36102/18202/9402
Package Dimensions
HM66AEB36102/18202/9402BP (BP-165A)
Preliminary
15.00 0.10 11 10 9 8 7 6 5 4 3 2 1
Unit: mm
Y A B C D E F G H J K L M N P R
index
14 x 1.00
17.00 0.10
10 x 1.00
0.25 C
0.32 0.05
1.40 0.06
C
165 x 0.50 0.05 0.20 M C A B 0.07 M C
0.15 C
Package Code JEDEC JEITA Mass (reference value)
Details of the part Y
BP-165A 0.7 g
Rev.0.01, Apr.28.2004, page 28 of 28
Revision History
HM66AEB36102/HM66AEB18202 HM66AEB9402 Data Sheet
Contents of Modification Page Description Initial issue
Rev.
Date
0.0 0.01
Dec. 18, 2002 Apr.28.2004
Change format issued by Renesas Technology Corp. HM66AEB9402: Change of pin names DQ0 to DQ1 DQ1 to DQ2 DQ2 to DQ3 DQ3 to DQ4 DQ4 to DQ5 DQ5 to DQ6 DQ6 to DQ7 DQ7 to DQ8 DQ8 to DQ0 4 Addition of Notes on Usage 5-6 Pin Descriptions SA0/SAn to SA0/SA SA0/SA: Change of Descriptions K, K: Change of Descriptions C, C: Change of Descriptions ZQ: Change of Descriptions DQ0 to DQn: Change of Descriptions VREF: Change of Descriptions NC: Change of Descriptions Block Diagram 7-8 Change of the figures Truth Table 9 DA(A1) to D(A1) DA(A2) to D(A2) QA(A1) to Q(A1) QA(A2) to Q(A2) Change of Notes3, 6 10-11 Byte Write Truth Table 0 to L 1 to H Bus Cycle State Diagram 11 Change of Notes1 Absolute Maximum Ratings 12 VIN, VI/O, VDD, VDDQ (Notes4) Maximum value: 2.9 V to 2.5 V Recommended DC Operating Conditions 12 Deletion of Notes2 Notes3 to Notes2 Change of Notes2 Addition of Notes3
Rev.
Date
Contents of Modification Page Description DC Characteristics (1st table) IDD (Max): x9, x18: 525/475/400/330/280 mA to 770/720/630/540/480 mA x36: 710/640/545/445/380 mA to 880/800/700/600/520 mA ISB1 (Max): x9, x18: 255/235/200/170/150 mA to 350/330/300/280/260 mA x36: 265/240/210/180/160 mA to 350/330/300/280/260 mA IDD, ISB1: Addition of Notes Deletion of Notes3 Notes4 to Notes3 Addition of Notes4 Notes1-5 are moved to DC Characteristics (2nd table) DC Characteristics (2nd table) Deletion of IOH, IOL Deletion of Notes5-7, 10 Notes1-4 to Notes6-9 Notes8-9 to Notes10-11 Capacitance Change of condition CI/O: Change of Parameter Change of Notes2 AC Characteristics Output load condition: Change of the figure VIH (AC), VIL (AC): Addition of Notes4 Addition of Notes2 Notes2-3 to Notes3-4 Change of Notes3 tKC reset, tCQHQV, tCQHQX: Addition of Notes7 tCHQZ, tCHQX1: Change of Parameter Remarks1 to Notes7 Change of Notes7 Remarks2-5 to Remarks1-4 Addition of Remarks5 Timing Waveforms Notes4 to Notes5 Addition of Notes4 TAP DC Operating Characteristics Addition of Notes4 TAP Controller Timing Diagram Change of the figure
0.01
Apr.28.2004
13
13
14
14 15
16 17
18
20 22
Rev.
Date
Contents of Modification Page Description
0.01
Apr.28.2004
23-24 TAP Controller Instruction Set SAMPLE(-PRELOAD) to SAMPLE(/PRELOAD) EXTEST, SAMPLE-Z, RESERVED, SAMPLE(/PRELOAD): Change of Description Addition of Notes3-4 24 ID Register Vendor JEDEC code: 00000000111 to 01000100011 25-26 Boundary Scan Order Change of Note 28 Package Dimensions Change of the figure of BP-165A
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2003, 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0

▲Up To Search▲

Price & Availability of HM66AEB18202

	To Download HM66AEB18202 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .